FPGAs are getting cheaper, a keyword that hits everyone’s sweet spot. They’re also being employed as host processing elements. The panel of technical experts will discuss how current programmable logic offerings help support the challenges and varieties of leading edge processing, and how the versatility of FPGAs contributes to maintaining an advantage for implementing leading edge algorithms that are still evolving. Panelists will also cover how designers are able to use an FPGA to lower the overall design cost and power consumption of a system by offloading heavy computations and using a less powerful processor or DPS.
Moderator: Robert Cravotta, Principal Analyst, Embedded Insights
Panelists:
Tom Hill, System Generator Product Manager, Xilinx
Travis Lanier, ARM
Tim Morin, Sr. Product Development Manager, Actel
Joe Rash, VP of Business Development, CebaTech
Imperas, which through the Open Virtual Platforms (OVP) is the de facto source for instruction accurate processor modeling and simulation, has announced a major release of new technology, the virtual platform simulator OVPsim. OVPsim has improved its industry leading performance by 50 percent and includes fast models of PowerPC processors, and a MIPS-based reference platform under SystemC/TLM-2.0 which boots both Linux and Mentor Graphic’s Nucleus RTOS.
Read more at Imperas.
Catch this video interview discussing GZIP IP and its uses in the industry.
CebaTech Inc., an innovative developer of advanced FPGA embedded system solutions, CebaFlex™, has announced the expansion of its CebaRIP library of rapidly tunable silicon intellectual property (IP) cores with new, multi-stream versions of its GZIP compression and GUNZIP decompression IP targeted specifically at data networking applications. The new cores are the first GZIP and GUNZIP IP cores to execute hundreds of thousands of data streams concurrently without performance degradation, in contrast to conventional cores that – at best – execute only a few data steams simultaneously before performance degrades. The new cores eliminate the need for multiple conventional IP cores or multiple, parallel software programmable processors.
Read more at CebaTech
